Performance evaluation of HPS and HPS+FPGA hardware architectures for an image processing system

• Cesar Arturo Niño Carmona Universidad Nacional de Piura. Perú. http://orcid.org/0000-0002-0981-0822
• Manuel Jesús Sánchez-Chero Universidad Nacional de Frontera. Perú. http://orcid.org/0000-0003-1646-3037
• Emanuel Ortiz Ortiz Universidad Nacional de Piura. Perú https://orcid.org/0000-0002-0125-9685
• Juan Carlos Sernaque Julca Universidad Nacional de Piura. Perú. https://orcid.org/0000-0002-3507-9340
• Cecilia Lizeth Risco Ipanaqué Universidad Nacional de Frontera. Perú http://orcid.org/0000-0002-7936-1495

DOI: https://doi.org/10.46925//rdluz.32.22

Keywords: Processing Algorithms; Hardware Architectures; SoC Platform; Performance; Image Processing

Abstract

The objective of this work was to evaluate the performance of hardware architectures: Hard Processor System (HPS) and the union of an HPS with a programmable gate array or FPGA (HPS + FPGA) for an image processing system. The following are evaluated: the execution time of the image processing algorithms and the energy consumption. For a SoC Platform, hardware design is performed at Verilog using the IP video cores of the Intel University Program (UP) - FPGA. The software for control and visualization of results using OpenCV is also developed. We worked with 320x240 pixels images. For a real time application it was observed an improvement of 38.8% in the execution time and a 6.85% higher consumption in the HPS+FPGA Architecture with respect to the HPS Architecture. The HPS+FPGA Architecture outperforms HPS and keeps power consumption low.

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